防爆波活门规格:Nand Flash 接口实验

下面一段话摘自S3C2440A数据手册Nand Flash controller一章：
In recent times, NOR flash memory gets high in price while an SDRAM and a NAND flash memory is comparatively economical , motivating some users to execute the boot code on a NAND flash and execute the main code on an SDRAM.
上面的话大意是由于Nor Flash价格比较贵，因而促使人们使用Nand Flash+SDRAM组合。
S3C2440A boot code can be executed on an external NAND flash memory. In order to support NAND flash boot loader, the S3C2440A is equipped with an internal SRAM buffer called ‘Steppingstone’. When booting, the first 4 KBytes of the NAND flash memory will be loaded into Steppingstone and the boot code loaded into Steppingstone will be executed。
上面的话很好的概括了Nand controller的作用。
Generally, the boot code will copy NAND flash content to SDRAM. Using hardware ECC, the NAND flash data validity will be checked. Upon the completion of the copy, the main program will be executed on the SDRAM.
这段话就是讲了怎样使用Nand 启动的方法。
具体的操作方式见下图：

上面的图少了special function register控制流，具体的可以参考，S3C2410的。
During reset, Nand flash controller will get information about the connected NAND flash through Pin status (NCON(Adv flash), GPG13(Page size), GPG14(Address cycle), GPG15(Bus width) – refer to PIN CONFIGURATION), After power-on or system reset is occurred, the NAND Flash controller load automatically the 4-KBytes boot loader codes. After loading the boot loader codes, the boot loader code in steppingstone is executed.
关于Steppgingstone手册里的一句话是这么讲的：
The NAND Flash controller uses Steppingstone as the buffer on booting and also you can use this area for another purpose
引脚配置（仅仅列出本开发板配置情况）：
OM[1:0] = 00: Enable NAND flash memory boot
NCON: NAND flash memory selection(Normal / Advance)
0: Normal NAND flash(256Words/512Bytes page size, 3/4 address cycle)
GPG13: NAND flash memory page capacitance selection
1: Page=512Bytes(NCON = 0) or Page=2KBytes(NCON = 1)
GPG14: NAND flash memory address cycle selection
1: 4 address cycle(NCON = 0) or 5 address cycle(NCON = 1)
GPG15: NAND flash memory bus width selection
0: 8-bit bus width
My Nand flash configuration setting
Parts
Page size/Total size
NCON0
GPG13
GPG14
GPG15
K9F1208
512Byte/512Mbit
0
1
1
0
NAND FLASH MEMORY TIMING

TACLS和TWRPH0和TWRPH1这三个参数控制的是Nand Flash信号线CLE和ALE与写控制信号nWE的时序关系。
SOFTWARE MODE
S3C2440A supports only software mode access. Using this mode, you can completely access the NAND flash memory. The NAND Flash Controller supports direct access interface with the NAND flash memory。
下面是通过寄存器操作Nand Flash的方法，操作的寄存器和相应Nand Flash的对应关系：
Writing to the command register = the NAND Flash Memory command cycle
Writing to the address register = the NAND Flash Memory address cycle
Writing to the data register = write data to the NAND Flash Memory (write cycle)
Reading from the data register = read data from the NAND Flash Memory (read cycle)
Reading main ECC registers and Spare ECC registers = read data from the NAND Flash Memory
In the software mode, you have to check the RnB status input pin by using polling or interrupt.
Data Register Configuration
8-bit NAND Flash Memory Interface
Register
Endian
Bit [31:24]
Bit [23:16]
Bit [15:8]
Bit [7:0]
NFDATA
little
4th I/O[ 7:0]
3rd I/O[ 7:0]
2nd I/O[ 7:0]
1st I/O[ 7:0]
下面是Nand Flash的memory mapping图，可以对照memory controller一章，可加深理解。

下面是nand Flash和S3C2440A的接口电路:

相应的引脚含义如下：

S3C2440A相应的pin：

ALE：Address latch enable
CLE：Command latch enable
nFCE：Nand flash chip enable
nFRE：Nand flash read enable
nFWE：Nand flash write enable
FRnB：Nand flash ready/busy
NCON：Nand flash configuration（上面已经有解释了）
Nand Flash（非线性存储器，即不是通过线性、连续的地址进行寻址）不同于Nor Flash（线性存储器，即通过连续的地址进行寻址），是通过指令对其进行读、写、块擦除等各种操作的，而指令又通过8位I/O端口进行传输，这样有效的减少了引脚的数量，也能保证不同容量在引脚、封装上的兼容，利于系统升级。
分析pin configuration的时候手册上有address cycle selection,这里分析它的原因-Nand Flash的寻址方式。Nand Flash存储容量以page、block为单位，64MB的Nand Flash共有4096个block，每个block有32个page，每个page包含512 Btyes+16Btye（冗余区，用于存放坏块标志、块逻辑地址页内数据的ECC checksum等）。具体见下图（K9f1208U0M）：

可以看出有效数据的存储单元有512Byte*32page*4096block=64MB，寻址需要9位Column address（512=2^9,即page内的offset），5位page address（32=2^5）和12位block address（4096=2^12）,共26为地址（64MB=2^26）
下图是K9f1208U0M的address cycle：

因为Nand Flash只能通过8位I/O port进行地址传送（即，总线的宽度是8位），所以上图要4个cycle才能完成寻址。如果是32MB一下的Nand Flash，那么最高使用A24就OK了，这样只要3个cycle addressing就能搞定。
NOTE：
上面的疑问column address是9位，为什么上面column address却是A0~A7？仔细看图会发现没有A8，这是因为Nand　Flash将一个page的512Byte分成了第一个half page和第二个half page，这half page有A0~A8寻址，再通过命令分别设置A8的值以确定寻址的是那个half page。