中药泡浴图片:一个8421码十进制计数器（异步置数）及七段数码管显示系统

一个8421码十进制计数器（异步置数）及七段数码管显示系统LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY counter10 IS    PORT( clk: IN STD_LOGIC;             load: IN STD_LOGIC;               din: IN STD_LOGIC_VECTOR(3 DOWNTO 0);             qout: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);                  c: OUT STD_LOGIC);END counter10; ARCHITECTURE art2 OF counter10 IS    SIGNAL temp: STD_LOGIC_VECTOR(3 DOWNTO 0);BEGIN     PROCESS(clk,load,din)     BEGIN         IF(load='0') THEN              temp<=din;         ELSIF(clk'EVENT AND clk='1') THEN              IF(temp="1001") THEN                    temp<="0000";              ELSE                    temp<=temp+1;              END IF;         END IF;    END PROCESS;    qout<=temp;    c<='1' WHEN temp="1001" ELSE         '0';END art2;   LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; ENTITY bcd ISPORT(           A:IN STD_LOGIC_VECTOR(3 DOWNTO 0);           Y:OUT STD_LOGIC_VECTOR(6 DOWNTO 0)          );END bcd; ARCHITECTURE art1 OF bcd ISBEGIN    Y<="1111110" WHEN A="0000" ELSE          "0110000" WHEN A="0001" ELSE          "1101101" WHEN A="0010" ELSE          "1111001" WHEN A="0011" ELSE          "0110011" WHEN A="0100" ELSE          "1011011" WHEN A="0101" ELSE          "0011111" WHEN A="0110" ELSE          "1110000" WHEN A="0111" ELSE          "1111111" WHEN A="1000" ELSE          "1110011" WHEN A="1001" ELSE          "0000000";END art1; LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY  counter10_bcd IS    PORT(clkin,clrin: IN STD_LOGIC;            yout: OUT STD_LOGIC_VECTOR(6 DOWNTO 0);             d: IN STD_LOGIC_VECTOR(3 DOWNTO 0)      );END counter10_bcd; ARCHITECTURE art3 OF counter10_bcd ISCOMPONENT counter10        PORT( clk: IN STD_LOGIC;              load: IN STD_LOGIC;               din: IN STD_LOGIC_VECTOR(3 DOWNTO 0);             qout: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);                  c: OUT STD_LOGIC);END COMPONENT;COMPONENT bcd      PORT(            A:IN STD_LOGIC_VECTOR(3 DOWNTO 0);           Y:OUT STD_LOGIC_VECTOR(6 DOWNTO 0)          );END COMPONENT;SIGNAL q: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL c1: STD_LOGIC;BEGINu1:counter10 PORT MAP(clk=>clkin,load=>clrin,din=>d,qout=>q,c=>c1);u2:bcd PORT MAP(A=>q,Y=>yout);END art3;