偶看新闻武进区公安局长张强:模拟IC电路设计注意的问题
来源：百度文库 编辑：偶看新闻 时间：2024/04/28 02:46:26
关于模拟设计的基本考虑
很多时候，我们在初期设计或者优化电路时，满脑子想的都是性能如何能一点一点提高，而忽略了所谓的模拟设计的一些基本考虑；待到版图设计时已经晚矣。那个时候再去修改基本设计无疑是不值得，要么耗费精力，要们前功尽弃。作为教训，如果我们能够在设计初期，就带着这些基本考虑，那么在选择基本器件的时候，就会有的放矢，知道一个大概的合理的选取范围，有利于版图设计和优化。
晶体管最小沟长为工艺最小特征尺寸的4-5倍，用来减小沟长调制效应。
2. Present art ofanalog design still uses the transistor in the saturation region. Soone should always keep Vgs of the Transistor 30% above the Vt.
目前模拟设计仍然是使晶体管工作在饱和区，故应使Vgs大于Vt约30%。
3. One should always split the big transistor into small transistors having width or length feature size < or = 15um.
应把大管分成小晶体管，使其宽/长特征尺寸<或=15um。
4. W/L Ratio oftransistors of the mirror circuit should be less than or equal to 5, toensure the proper matching of the transistors in the layout. Otherwise,it results to the Systematic Offset in the circuit.
电流镜电路的晶体管的w/l比应小于或等于5，以保证较好的Matching,否则会有系统失调。
5. One should makeall the required pins in the schematic before generating the layoutview. Because it’s difficult to add a pin in the layout view. All IOpins should be a metal2 pins whereas VDD and Ground should be metal1pins
在电路中画出所有的管脚（pin），之后才作layout。因为在layout中增加一个pin是比较困难的。所有的IO pin应该用metal2 pin，VDD和GND用metal1。
6. One should firstsimulate the circuit with the typical model parameters of the devices.Since Vt of the transistor can be anything between Vt(Typical) -/+ 20%.So we check our circuit for the extreme cases i.e. Vt+20%, Vt-20%. Atransistor having Vt-20% is called a fast transistor and transistorhaving Vt+20% is called slow transistor. It’s just a way todifferentiate them. So with these fast and slow transistor models wemake four combination called nfpf, nfps, nspf, nsps, which are known asprocess corners. Now, once we are satisfied with the circuitperformance with typical models than we check it in different processcorners, to take the process variation into account. Vt is just oneexample of the process variation there are others parameter too.
首先先用tt做电路仿真。考虑Vt有+20% (slow)和-20% (fast),需要对工艺角考虑，FF，SS，FS，SF。除Vt，其他工艺参数也会有变化。
7. Its thumb rulethat poly resistance has a 20% process variation whereas wellresistance has got 10%. But the poly resistance has got lowertemperature coefficient and lower Sheet Resistance than well resistanceSo we choose the resistance type depending upon the requirements. PolyCapacitance has got a process variation of 10%.
多晶硅电阻大约有20%的工艺变化，而阱区电阻变化约为10%。但多晶硅电阻有较低的温度系数和低的方块电阻，应根据需要来选择电阻。多晶硅电容约有10%工艺变化。
8. One should also check the circuit performance with the temperature variation. We usually do it for the range of -40C to 85C.
需考虑温度变化对电路性能的影响，通常在-40C到85C范围。
9. One should take the parasitic capacitance into account wherever one is making an overlap with metal layers or wells.
有覆盖金属层或阱区时，须考虑寄生电容。
10. In Layout, all transistors should be placed in one direction, to provide the same environment to all the transistors.
Layout中，所有晶体管统一摆放方向，使有相同的环境。
11. One should place all transistor in layout with a due care to the pin position before start routing them.
在对晶体管布局布线之前，考虑Pin的位置。
12. One should always use the Metal 1 for horizontal routing and Metal 2 for the vertical routing as far as possible.
尽量使用metal1横向布线，metal2纵向布线半导体。
13. One shouldnever use POLY as routing layer when the interconnects carries acurrent. One can have a short gate connection using poly.
在互连用来传送电流时，不要用Poly来做互连。可以用poly做短的栅连接。
14. One should try to avoid running metal over poly gate. As this cause to increase in parasitic capacitance.
避免金属在多晶硅栅上走线，会增加寄生电容。
15. Current in all the transistor and resistor part should flow in the same direction.
所有晶体管和电阻有相同的电流走向。
16. One should dothe Power(VDD & GND) routing in top layer metal (metal5 only).Because Top layer metals are usually thicker and wider and so has lowresistance.
在最上层金属做电源（VDD和GND）布线。因为最上层金属通常更厚、更宽，因而电阻较小。
17. One should always merge drain and source of transistor (of same type) connected together.
merge连接的Source和Drain。
18. To minimize theprocess variation in the Resistor value one should always take theresistor’s width three to four times of the default value. we do it todecrease the value of differential of R(L)
为减小工艺变化对电阻影响，应使电阻的宽度为默认值的3-4倍半导体。
19. One should cover the resistance with metal layer, to avoid the damaged during the wafer level testing.
用金属覆盖电阻，避免wafer级测试时的损伤。
20. One shouldalways make a Common Centroid structure for the matched transistor inthe layout. Each differential pair transistor should be divide intofour transistors and should be placed in two rows common centroidstructure. One may use the linear common centroid structure for thecurrent mirror circuit.
对匹配的晶体管用共中心的结构
*差分对管，分割为4管，2*2排列，共中心
可用线形共中心
21. It’s advisable to put a dummy layers around the resistance and the capacitance to avoid the erosion at the time of etching.
建议在电阻和电容周围作dummy。
22. One should always have a Guard Ring around the differential pair.
在差分对周围作保护环。
23. Always put a Guard Ring around the N-well and P-well.
在N阱和P阱作保护环。
24. Thumb rule for the metal current density is 0.8mA/um. It’s larger for the top most metal layer.
金属电流密度0.8mA/um，最上层金属可以更大半导体。
25. To avoid theLatch-up, one should always make the PN junction reverse biased i.e. InNWELL should be connected to positive power supply (VDD) and PWELLshould be connected to negative power supply (GND). Designers do it tomake the leakage current small.
为避免Latch-up，应使PN结反偏，如N-Well应连到正电源，P-Well应连到负电源。这样可减小漏电。
26.It’s always a good practice to use an info-text layer to put the nameof the device on the top of it in layout and have a net-name for everynets in schematic. Designer should put the pin name on the top of thepin with same metal-txt layer because hercuels takes the net-name from metal-txt only whereas Diva takes from the pin-name.
在layout中用info-text标明器件名称，在schematic中标明net。用相同的metal-txt层标明pin。
27. Cadence SPICEsimulator take vdd! & gnd! as a global VDD and GND net i.e. any netending with ‘ !’ is considered as a global net.
Cadence 模拟工具对以‘!’结尾的net认为全局net。
28. Transistor Equation: 基本晶体管方程
